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Richard Henderson authored
Failure to do so results in the tcg optimizer sign-extending any constant fold from 32-bits. This turns out to be visible in the RISC-V testsuite using a host that emits these opcodes (e.g. any non-x86_64). Reported-by:
Michael Clark <mjc@sifive.com> Reviewed-by:
Emilio G. Cota <cota@braap.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
f2f1dde7
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aarch64 | ||
arm | ||
i386 | ||
mips | ||
ppc | ||
s390 | ||
sparc | ||
tci | ||
LICENSE | ||
README | ||
TODO | ||
optimize.c | ||
tcg-common.c | ||
tcg-gvec-desc.h | ||
tcg-ldst.inc.c | ||
tcg-mo.h | ||
tcg-op-gvec.c | ||
tcg-op-gvec.h | ||
tcg-op-vec.c | ||
tcg-op.c | ||
tcg-op.h | ||
tcg-opc.h | ||
tcg-pool.inc.c | ||
tcg.c | ||
tcg.h | ||
tci.c |