1. 04 May, 2017 6 commits
    • Stafford Horne's avatar
      target/openrisc: Support non-busy idle state using PMR SPR · f4d1414a
      Stafford Horne authored
      The OpenRISC architecture has the Power Management Register (PMR)
      special purpose register to manage cpu power states.  The interesting
      modes are:
      
       * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt
       * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt
       * Suspend Model (SUME) - Stop cpu and all units - wake on reset
      
      The linux kernel will set DME when idle.
      
      This patch implements the PMR SPR and halts the qemu cpu when there is a
      change to DME or SME.  This means that openrisc qemu in no longer peggs
      a host cpu at 100%.
      
      In order for this to work we need to kick the CPU when timers are
      expired.  Update the cpu timer to kick the cpu upon each timer event.
      Reviewed-by: 's avatarRichard Henderson <rth@twiddle.net>
      Signed-off-by: 's avatarStafford Horne <shorne@gmail.com>
      f4d1414a
    • Stafford Horne's avatar
      target/openrisc: Remove duplicate features property · 48a1b62b
      Stafford Horne authored
      The features property has stored the exact same thing as the cpucfgr
      spr. Remove the feature enum and property as it is not needed.
      
      In order to preserve the behavior or keeping features accross reset this
      patch moves cpucfgr into the non reset region of the state struct.  Since
      the cpucfgr is read only this means we only need to sset cpucfgr once
      during class init.
      Signed-off-by: 's avatarStafford Horne <shorne@gmail.com>
      48a1b62b
    • Stafford Horne's avatar
      target/openrisc: Implement full vmstate serialization · acf57591
      Stafford Horne authored
      Previously serialization did not persist the tlb, timer, pic and other
      key state items.  This meant snapshotting and restoring a running os
      would crash. After adding these I am able to take snapshots of a
      running linux os and restore at a later time.
      
      I am currently not trying to maintain capatibility with older versions
      as I do not believe this really worked before or anyone used it.
      Signed-off-by: 's avatarStafford Horne <shorne@gmail.com>
      acf57591
    • Stafford Horne's avatar
      target/openrisc: implement shadow registers · d89e71e8
      Stafford Horne authored
      Shadow registers are part of the openrisc spec along with sr[cid], as
      part of the fast context switching feature.  When exceptions occur,
      instead of having to save registers to the stack if enabled the CID will
      increment and a new set of registers will be available.
      
      This patch only implements shadow registers which can be used as extra
      scratch registers via the mfspr and mtspr if required.  This is
      implemented in a way where it would be easy to add on the fast context
      switching, currently cid is hardcoded to 0.
      
      This is need for openrisc linux smp kernels to boot correctly.
      Signed-off-by: 's avatarStafford Horne <shorne@gmail.com>
      d89e71e8
    • Stafford Horne's avatar
      target/openrisc: add numcores and coreid support · ef3f5b9e
      Stafford Horne authored
      These are used to identify the processor in SMP system.  Their
      definition has been defined in verilog cores but it not yet part of the
      spec but it will be soon.
      
      The proposal for this is available:
        https://openrisc.io/proposals/core-identifier-and-number-of-coresReviewed-by: 's avatarRichard Henderson <rth@twiddle.net>
      Signed-off-by: 's avatarStafford Horne <shorne@gmail.com>
      ef3f5b9e
    • Stafford Horne's avatar
      target/openrisc: Fixes for memory debugging · 461a4b94
      Stafford Horne authored
      When debugging in gdb you might want to inspect instructions in mapped
      pages or in exception vectors like 0x800 etc.  This was previously not
      possible in qemu since the *get_phys_page_debug() routine only looked
      into the data tlb.
      
      Change to fall back to look into instruction tlb and plain physical
      pages.
      Reviewed-by: 's avatarRichard Henderson <rth@twiddle.net>
      Signed-off-by: 's avatarStafford Horne <shorne@gmail.com>
      461a4b94
  2. 21 Apr, 2017 2 commits
    • Tim 'mithro' Ansell's avatar
      target/openrisc: Implement EPH bit · 3fee028d
      Tim 'mithro' Ansell authored
      Exception Prefix High (EPH) control bit of the Supervision Register
      (SR).
      
      The significant bits (31-12) of the vector offset address for each
      exception depend on the setting of the Supervision Register (SR)'s EPH
      bit and the Exception Vector Base Address Register (EVBAR).
      
      If SR[EPH] is set, the vector offset is logically ORed with the offset
      0xF0000000.
      
      This means if EPH is;
       * 0 - Exceptions vectors start at EVBAR
       * 1 - Exception vectors start at EVBAR | 0xF0000000
      Signed-off-by: 's avatarTim 'mithro' Ansell <mithro@mithis.com>
      Signed-off-by: 's avatarStafford Horne <shorne@gmail.com>
      3fee028d
    • Tim 'mithro' Ansell's avatar
      target/openrisc: Implement EVBAR register · 356a2db3
      Tim 'mithro' Ansell authored
      Exception Vector Base Address Register (EVBAR) - This optional register
      can be used to apply an offset to the exception vector addresses.
      
      The significant bits (31-12) of the vector offset address for each
      exception depend on the setting of the Supervision Register (SR)'s EPH
      bit and the Exception Vector Base Address Register (EVBAR).
      
      Its presence is indicated by the EVBARP bit in the CPU Configuration
      Register (CPUCFGR).
      Signed-off-by: 's avatarTim 'mithro' Ansell <mithro@mithis.com>
      Signed-off-by: 's avatarStafford Horne <shorne@gmail.com>
      356a2db3
  3. 13 Feb, 2017 21 commits
  4. 13 Jan, 2017 2 commits
    • Alex Bennée's avatar
      cputlb: drop flush_global flag from tlb_flush · d10eb08f
      Alex Bennée authored
      We have never has the concept of global TLB entries which would avoid
      the flush so we never actually use this flag. Drop it and make clear
      that tlb_flush is the sledge-hammer it has always been.
      Signed-off-by: 's avatarAlex Bennée <alex.bennee@linaro.org>
      Reviewed-by: 's avatarRichard Henderson <rth@twiddle.net>
      [DG: ppc portions]
      Acked-by: 's avatarDavid Gibson <david@gibson.dropbear.id.au>
      d10eb08f
    • Alex Bennée's avatar
      qom/cpu: move tlb_flush to cpu_common_reset · 1f5c00cf
      Alex Bennée authored
      It is a common thing amongst the various cpu reset functions want to
      flush the SoftMMU's TLB entries. This is done either by calling
      tlb_flush directly or by way of a general memset of the CPU
      structure (sometimes both).
      
      This moves the tlb_flush call to the common reset function and
      additionally ensures it is only done for the CONFIG_SOFTMMU case and
      when tcg is enabled.
      
      In some target cases we add an empty end_of_reset_fields structure to the
      target vCPU structure so have a clear end point for any memset which
      is resetting value in the structure before CPU_COMMON (where the TLB
      structures are).
      
      While this is a nice clean-up in general it is also a precursor for
      changes coming to cputlb for MTTCG where the clearing of entries
      can't be done arbitrarily across vCPUs. Currently the cpu_reset
      function is usually called from the context of another vCPU as the
      architectural power up sequence is run. By using the cputlb API
      functions we can ensure the right behaviour in the future.
      Signed-off-by: 's avatarAlex Bennée <alex.bennee@linaro.org>
      Reviewed-by: 's avatarRichard Henderson <rth@twiddle.net>
      Reviewed-by: 's avatarDavid Gibson <david@gibson.dropbear.id.au>
      1f5c00cf
  5. 10 Jan, 2017 1 commit
  6. 20 Dec, 2016 1 commit
    • Thomas Huth's avatar
      Move target-* CPU file into a target/ folder · fcf5ef2a
      Thomas Huth authored
      We've currently got 18 architectures in QEMU, and thus 18 target-xxx
      folders in the root folder of the QEMU source tree. More architectures
      (e.g. RISC-V, AVR) are likely to be included soon, too, so the main
      folder of the QEMU sources slowly gets quite overcrowded with the
      target-xxx folders.
      To disburden the main folder a little bit, let's move the target-xxx
      folders into a dedicated target/ folder, so that target-xxx/ simply
      becomes target/xxx/ instead.
      
      Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
      Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
      Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
      Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
      Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
      Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
      Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
      Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
      Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
      Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
      Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part]
      Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
      Signed-off-by: 's avatarThomas Huth <thuth@redhat.com>
      fcf5ef2a