- 31 Jan, 2018 13 commits
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Helge Deller authored
Now that we have the prerequisites in target/hppa/, implement the hardware for a PA7100LC. This also enables build for hppa-softmmu. Signed-off-by:
Helge Deller <deller@gmx.de> [rth: Since it is all new code, squashed all branch development withing hw/hppa/ to a single patch.] Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
This is an extension to the base ISA, but we can use this in the kernel idle loop to reduce the host cpu time consumed. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Helge Deller authored
Signed-off-by:
Helge Deller <deller@gmx.de> Message-Id: <20180102203145.GA17059@ls3530.fritz.box> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Helge Deller authored
Signed-off-by:
Helge Deller <deller@gmx.de> Message-Id: <20171212212319.GA31494@ls3530.fritz.box> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
HP-UX 10.20 CD contains "add r0, r0, r27" in a delay slot, which uses at least 5 temps. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Unknown why this works, but if we return EXCP_ITLB_MISS we will triple-fault the first userland instruction fetch. Is it something to do with having a combined I/DTLB? Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Linux sets sr4-sr7 all to the same value, which means that we need not do any runtime computation to find out what space to use in forming the GVA. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Helge Deller authored
Real hardware would use an external device to control the power. But for the moment let's invent instructions in reserved space, to be used by our custom firmware. Signed-off-by:
Helge Deller <deller@gmx.de> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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- 30 Jan, 2018 27 commits
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
We now have all of the TLB manipulation instructions. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
The TLB can now be populated, but it cannot yet be cleared. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
However since HPPA has a software-managed TLB, and the relevant TLB manipulation instructions are not implemented, this does not actually do anything. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Any one TB will have only one space value. If we change spaces, we change TBs. Thus BE and BEV must exit the TB immediately. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
These instructions force the destination privilege level of the branch destination to be no higher than current. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
This changes the system virtual address width to 64-bit and incorporates the space registers into load/store operations. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
While the E bit is only used for pa2.0 mfctl,w from sar, the otherwise reserved bit does not appear to be decoded. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Not used where they should be yet, but we can copy them. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Most aspects of privilege are not yet handled. But this gives us the start from which to begin checking. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
For system mode, we will need 64-bit virtual addresses even when we have 32-bit register sizes. Since the rest of QEMU equates TARGET_LONG_BITS with the address size, redefine everything related to register size in terms of a new TARGET_REGISTER_BITS. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
We don't actually do anything with most of the bits yet, but at least they have names and we have somewhere to store them. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Helge Deller authored
With the addition of default-configs/hppa-softmmu.mak, this will compile. It is not enabled with this patch, however. Signed-off-by:
Helge Deller <deller@gmx.de> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Peter Maydell authored
Merge tpm 2018/01/26 v2 # gpg: Signature made Mon 29 Jan 2018 22:20:05 GMT # gpg: using RSA key 0x75AD65802A0B4211 # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211 * remotes/stefanberger/tags/pull-tpm-2018-01-26-2: tpm: add CRB device tpm: report backend request error tpm: replace GThreadPool with AIO threadpool tpm: lookup cancel path under tpm device class tpm: fix alignment issues tpm: Set the flags of the CMD_INIT command to 0 Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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