- 16 Feb, 2018 3 commits
-
-
Mark Cave-Ayland authored
Signed-off-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
-
Mark Cave-Ayland authored
Signed-off-by:
-
Mark Cave-Ayland authored
Add the relevant hooks as required for the MacOS timer calibration and delayed SR interrupt. Signed-off-by:
-
- 15 Feb, 2018 27 commits
-
-
Peter Maydell authored
target-arm queue: * aspeed: code cleanup to use unimplemented_device * preparatory work for 'raspi3' RaspberryPi 3 machine model * more SVE prep work * v8M: add minor missing registers * v7M: fix bug where we weren't migrating v7m.other_sp * v7M: fix bugs in handling of interrupt registers for external interrupts beyond 32 # gpg: Signature made Thu 15 Feb 2018 18:34:40 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180215-1: raspi: Raspberry Pi 3 support bcm2836: Make CPU type configurable target/arm: Implement v8M MSPLIM and PSPLIM registers target/arm: Migrate v7m.other_sp target/arm: Add AIRCR to vmstate struct hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions target/arm: Implement writing to CONTROL_NS for v8M hw/intc/armv7m_nvic: Implement SCR hw/intc/armv7m_nvic: Implement cache ID registers hw/intc/armv7m_nvic: Implement v8M CPPWR register hw/intc/armv7m_nvic: Implement M profile cache maintenance ops hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC target/arm: Handle SVE registers when using clear_vec_high target/arm: Enforce access to ZCR_EL at translation target/arm: Suppress TB end for FPCR/FPSR target/arm: Enforce FP access to FPCR/FPSR target/arm: Remove ARM_CP_64BIT from ZCR_EL registers hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io hw/arm/aspeed: directly map the serial device to the system address space Signed-off-by:Peter Maydell <peter.maydell@linaro.org>
-
Pekka Enberg authored
This patch adds Raspberry Pi 3 support to hw/arm/raspi.c. The differences to Pi 2 are: - Firmware address - Board ID - Board revision The CPU is different too, but that's going to be configured as part of the machine default CPU when we introduce a new machine type. The patch was written from scratch by me but the logic is similar to Zoltán Baldaszti's previous work, which I used as a reference (with permission from the author): https://github.com/bztsrc/qemu-raspi3Signed-off-by:
Pekka Enberg <penberg@iki.fi> [PMM: fixed trailing whitespace on one line] Reviewed-by:
-
Pekka Enberg authored
This patch adds a "cpu-type" property to BCM2836 SoC in preparation for reusing the code for the Raspberry Pi 3, which has a different processor model. Signed-off-by:
-
Peter Maydell authored
The v8M architecture includes hardware support for enforcing stack pointer limits. We don't implement this behaviour yet, but provide the MSPLIM and PSPLIM stack pointer limit registers as reads-as-written, so that when we do implement the checks in future this won't break guest migration. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-12-peter.maydell@linaro.org
-
Peter Maydell authored
In commit abc24d86 we accidentally broke migration of the stack pointer value for the mode (process, handler) the CPU is not currently running as. (The commit correctly removed the no-longer-used v7m.current_sp flag from the VMState but also deleted the still very much in use v7m.other_sp SP value field.) Add a subsection to migrate it again. (We don't need to care about trying to retain compatibility with pre-abc24d86 versions of QEMU, because that commit bumped the version_id and we've since bumped it again a couple of times.) Signed-off-by:
-
Peter Maydell authored
In commit commit 3b2e9344 we added support for the AIRCR register holding state, but forgot to add it to the vmstate structs. Since it only holds r/w state if the security extension is implemented, we can just add it to vmstate_m_security. Signed-off-by:
-
Peter Maydell authored
In many of the NVIC registers relating to interrupts, we have to convert from a byte offset within a register set into the number of the first interrupt which is affected. We were getting this wrong for: * reads of NVIC_ISPR<n>, NVIC_ISER<n>, NVIC_ICPR<n>, NVIC_ICER<n>, NVIC_IABR<n> -- in all these cases we were missing the "* 8" needed to convert from the byte offset to the interrupt number (since all these registers use one bit per interrupt) * writes of NVIC_IPR<n> had the opposite problem of a spurious "* 8" (since these registers use one byte per interrupt) Signed-off-by:
-
Peter Maydell authored
In commit 50f11062 we added support for MSR/MRS access to the NS banked special registers, but we forgot to implement the support for writing to CONTROL_NS. Correct the omission. Signed-off-by:
-
Peter Maydell authored
We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Signed-off-by:
-
Peter Maydell authored
M profile cores have a similar setup for cache ID registers to A profile: * Cache Level ID Register (CLIDR) is a fixed value * Cache Type Register (CTR) is a fixed value * Cache Size ID Registers (CCSIDR) are a bank of registers; which one you see is selected by the Cache Size Selection Register (CSSELR) The only difference is that they're in the NVIC memory mapped register space rather than being coprocessor registers. Implement the M profile view of them. Since neither Cortex-M3 nor Cortex-M4 implement caches, we don't need to update their init functions and can leave the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero. Newer cores (like the Cortex-M33) will want to be able to set these ID registers to non-zero values, though. Signed-off-by:
-
Peter Maydell authored
The Coprocessor Power Control Register (CPPWR) is new in v8M. It allows software to control whether coprocessors are allowed to power down and lose their state. QEMU doesn't have any notion of power control, so we choose the IMPDEF option of making the whole register RAZ/WI (indicating that no coprocessors can ever power down and lose state). Signed-off-by:
-
Peter Maydell authored
For M profile cores, cache maintenance operations are done by writing to special registers in the system register space. For QEMU, cache operations are always NOPs, since we don't implement the cache. Implementing these explicitly avoids a spurious LOG_GUEST_ERROR when the guest uses them. Signed-off-by:
-
Peter Maydell authored
The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had misimplemented this as making the bits RAZ/WI from both Secure and NonSecure states. Fix this bug by checking attrs.secure so that Secure code can pend and unpend NMIs. Signed-off-by:
-
Peter Maydell authored
Instead of hardcoding the values of M profile ID registers in the NVIC, use the fields in the CPU struct. This will allow us to give different M profile CPU types different ID register values. This commit includes the addition of the missing ID_ISAR5, which exists as RES0 in both v7M and v8M. (The values of the ID registers might be wrong for the M4 -- this commit leaves the behaviour there unchanged.) Signed-off-by:
-
Richard Henderson authored
When storing to an AdvSIMD FP register, all of the high bits of the SVE register are zeroed. Therefore, call it more often with is_q as a parameter. Signed-off-by:
-
Richard Henderson authored
This also makes sure that we get the correct ordering of SVE vs FP exceptions. Signed-off-by:
-
Richard Henderson authored
Nothing in either register affects the TB. Signed-off-by:
-
Richard Henderson authored
Signed-off-by:
-
Richard Henderson authored
Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied. Signed-off-by:
-
Philippe Mathieu-Daudé authored
(qemu) info mtree address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom - 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io + 000000001e600000-000000001e7fffff (prio -1000, i/o): aspeed_soc.io 000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc 000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1 000000001e631000-000000001e6310ff (prio 0, i/o): aspeed.smc.ast2500-spi2 Signed-off-by:Cédric Le Goater <clg@kaod.org> Reviewed-by:
Andrew Jeffery <andrew@aj.id.au> Message-id: 20180209085755.30414-3-f4bug@amsat.org Signed-off-by:
-
Philippe Mathieu-Daudé authored
(qemu) info mtree address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io - 000000001e784000-000000001e78401f (prio 0, i/o): serial 000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc 000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1 [...] 000000001e720000-000000001e728fff (prio 0, ram): aspeed.sram 000000001e782000-000000001e782fff (prio 0, i/o): aspeed.timer + 000000001e784000-000000001e78401f (prio 0, i/o): serial 000000001e785000-000000001e78501f (prio 0, i/o): aspeed.wdt 000000001e785020-000000001e78503f (prio 0, i/o): aspeed.wdt Signed-off-by: -
Peter Maydell authored
Pull request v2: * Dropped Fam's git-publish series because there is still ongoing discussion # gpg: Signature made Thu 15 Feb 2018 09:42:03 GMT # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: misc: fix spelling ratelimit: don't align wait time with slices vl: pause vcpus before stopping iothreads Signed-off-by: -
Peter Maydell authored
Various improvements to the qtest checks: - Clean-ups by Eric Blake with regards to the global_qtest variable - Some more test cases for the boot-serial tester - Re-activation of the m48t59-test # gpg: Signature made Wed 14 Feb 2018 11:07:44 GMT # gpg: using RSA key 2ED9D774FE702DB5 # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" # gpg: aka "Thomas Huth <thuth@redhat.com>" # gpg: aka "Thomas Huth <huth@tuxfamily.org>" # gpg: aka "Thomas Huth <th.huth@posteo.de>" # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth/tags/pull-request-2018-02-14: tests/m48t59: Use the m48t59 test on ppc, too tests/Makefile: Derive check-qtest-ppc64-y from check-qtest-ppc-y tests/m48t59: Make the test independent of global_qtest tests/m48t59: Fix and re-enable the test for sparc tests/boot-serial-test: Add support for the aarch64 virt machine tests/boot-serial: Add tests for PowerPC Mac machines tests/boot-serial: Enable the boot-serial test on SPARC machines, too wdt_ib700-test: Drop dependence on global_qtest tests/boot-sector: Drop dependence on global_qtest qmp-test: Drop dependence on global_qtest libqos: Use explicit QTestState for remaining libqos operations libqos: Use explicit QTestState for ahci operations libqos: Use explicit QTestState for i2c operations libqos: Use explicit QTestState for rtas operations libqos: Use explicit QTestState for fw_cfg operations libqos: Track QTestState with QPCIBus libqtest: Use qemu_strtoul() tests: Clean up wait for event Signed-off-by: -
Peter Maydell authored
# gpg: Signature made Wed 14 Feb 2018 10:37:02 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.12-pull-request: m68k: implement movep instruction Signed-off-by: -
Marc-André Lureau authored
s/pupulate/populate Signed-off-by:
Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by:
Stefan Hajnoczi <stefanha@redhat.com>
-
Wolfgang Bumiller authored
It is possible for rate limited writes to keep overshooting a slice's quota by a tiny amount causing the slice-aligned waiting period to effectively halve the rate. Signed-off-by:
Wolfgang Bumiller <w.bumiller@proxmox.com> Reviewed-by:
Alberto Garcia <berto@igalia.com> Message-id: 20180207071758.6818-1-w.bumiller@proxmox.com Signed-off-by:
-
Stefan Hajnoczi authored
Commit dce8921b ("iothread: Stop threads before main() quits") introduced iothread_stop_all() to avoid the following virtio-scsi assertion failure: assert(blk_get_aio_context(d->conf.blk) == s->ctx); Back then the assertion failed because when bdrv_close_all() made d->conf.blk NULL, blk_get_aio_context() returned the global AioContext instead of s->ctx. The same assertion can still fail today when vcpus submit new I/O requests after iothread_stop_all() has moved the BDS to the global AioContext. This patch hardens the iothread_stop_all() approach by pausing vcpus before calling iothread_stop_all(). Note that the assertion failure is a race condition. It is not possible to reproduce it reliably. Signed-off-by:
-
- 14 Feb, 2018 10 commits
-
-
Thomas Huth authored
The ref405ep machine has a memory-mapped m48t59 device, so we can run the m48t59 test on this machine, too. Signed-off-by:Thomas Huth <thuth@redhat.com>
-
Thomas Huth authored
ppc64 is a superset of ppc, so the ppc64 tests should include all the ppc tests. Signed-off-by: -
Thomas Huth authored
Stop using the functions that require global_qtest here and pass around the QTestState instead (global_qtest should finally get removed since this causes problems with tests running in parallel). Reviewed-by:
Eric Blake <eblake@redhat.com> Signed-off-by:
-
Thomas Huth authored
The m48t59 test has been disabled in commit baeddded ("sparc: disable qtest in make check"), likely due to some timing issues in the bcd_check_time tests which might fail if it gets interrupted for too long. It should be OK to re-enable this test if we make sure that we do not run it on timing-sensitive machines, thus it should be OK if we only run it in the g_test_slow() mode. Additionally, there are two other issues: First, the test can not run so easily on sparc64 anymore, since commit f3b18f35 ("sun4u: switch m48t59 NVRAM to MMIO access") moved the m48t59 device to the ebus instead, and for this you first have to set up the corresponding PCI device (which is currently not possible from within the m48t59 test). So we can only re-enable this test on sparc, but not the sparc64 target. Second, the fuzzing test is executed before the bcd-check-time test (due to the naming of the tests), without having the base address set up properly, so the fuzzing test does not really check anything at all. Fix it by setting up the base address from the main function already and by moving the qtest_start() to the tests themselves, so that each test starts with a clean environment (since after the fuzzing, the clock is unusable for the bcd-check-time test). Signed-off-by:
-
Wei Huang authored
This patch adds a small binary kernel to test aarch64 virt machine's UART. Signed-off-by:
Wei Huang <wei@redhat.com> Reviewed-by:
-
Thomas Huth authored
OpenBIOS prints out the CPU type on these machine types, so we can use this string to test whether the CPU detection is working correctly. Acked-by:
-
Thomas Huth authored
OpenBIOS prints out the name of the detected CPU here, so looking for this string is a nice test to verify that the CPU detection is still working correctly. Acked-by:
-
Eric Blake authored
As a general rule, we prefer avoiding implicit global state because it makes code harder to safely copy and paste without thinking about the global state. Improve this test to be explicit about the state. Signed-off-by:
-
Eric Blake authored
As a general rule, we prefer avoiding implicit global state because it makes code harder to safely copy and paste without thinking about the global state. Adjust the helper code to use explicit state instead, and update all callers. Fix some trailing whitespace while touching the file. Signed-off-by:
Michael S. Tsirkin <mst@redhat.com> Signed-off-by:
-
Eric Blake authored
As a general rule, we prefer avoiding implicit global state because it makes code harder to safely copy and paste without thinking about the global state. Although qmp-test does not maintain parallel qtest connections, it was the last test assigning to global_qtest. It's just as easy to be explicit about the state; once all tests have been cleaned up, a later patch can then get rid of global_qtest and a layer of wrappers in libqtest. Signed-off-by:
-
