Commit fcf5ef2a authored by Thomas Huth's avatar Thomas Huth

Move target-* CPU file into a target/ folder

We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.

Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part]
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
Signed-off-by: 's avatarThomas Huth <thuth@redhat.com>
parent 82ecffa8
......@@ -106,7 +106,7 @@ F: include/fpu/
Alpha
M: Richard Henderson <rth@twiddle.net>
S: Maintained
F: target-alpha/
F: target/alpha/
F: hw/alpha/
F: tests/tcg/alpha/
F: disas/alpha.c
......@@ -115,7 +115,7 @@ ARM
M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
S: Maintained
F: target-arm/
F: target/arm/
F: hw/arm/
F: hw/cpu/a*mpcore.c
F: include/hw/cpu/a*mpcore.h
......@@ -126,7 +126,7 @@ F: disas/libvixl/
CRIS
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
S: Maintained
F: target-cris/
F: target/cris/
F: hw/cris/
F: include/hw/cris/
F: tests/tcg/cris/
......@@ -135,7 +135,7 @@ F: disas/cris.c
LM32
M: Michael Walle <michael@walle.cc>
S: Maintained
F: target-lm32/
F: target/lm32/
F: disas/lm32.c
F: hw/lm32/
F: hw/*/lm32_*
......@@ -147,13 +147,13 @@ F: tests/tcg/lm32/
M68K
M: Laurent Vivier <laurent@vivier.eu>
S: Maintained
F: target-m68k/
F: target/m68k/
F: disas/m68k.c
MicroBlaze
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
S: Maintained
F: target-microblaze/
F: target/microblaze/
F: hw/microblaze/
F: disas/microblaze.c
......@@ -161,7 +161,7 @@ MIPS
M: Aurelien Jarno <aurelien@aurel32.net>
M: Yongbok Kim <yongbok.kim@imgtec.com>
S: Maintained
F: target-mips/
F: target/mips/
F: hw/mips/
F: hw/misc/mips_*
F: hw/intc/mips_gic.c
......@@ -176,7 +176,7 @@ F: disas/mips.c
Moxie
M: Anthony Green <green@moxielogic.com>
S: Maintained
F: target-moxie/
F: target/moxie/
F: disas/moxie.c
F: hw/moxie/
F: default-configs/moxie-softmmu.mak
......@@ -184,7 +184,7 @@ F: default-configs/moxie-softmmu.mak
OpenRISC
M: Jia Liu <proljc@gmail.com>
S: Maintained
F: target-openrisc/
F: target/openrisc/
F: hw/openrisc/
F: tests/tcg/openrisc/
......@@ -193,7 +193,7 @@ M: David Gibson <david@gibson.dropbear.id.au>
M: Alexander Graf <agraf@suse.de>
L: qemu-ppc@nongnu.org
S: Maintained
F: target-ppc/
F: target/ppc/
F: hw/ppc/
F: include/hw/ppc/
F: disas/ppc.c
......@@ -202,14 +202,14 @@ S390
M: Richard Henderson <rth@twiddle.net>
M: Alexander Graf <agraf@suse.de>
S: Maintained
F: target-s390x/
F: target/s390x/
F: hw/s390x/
F: disas/s390.c
SH4
M: Aurelien Jarno <aurelien@aurel32.net>
S: Odd Fixes
F: target-sh4/
F: target/sh4/
F: hw/sh4/
F: disas/sh4.c
F: include/hw/sh4/
......@@ -218,7 +218,7 @@ SPARC
M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
M: Artyom Tarasenko <atar4qemu@gmail.com>
S: Maintained
F: target-sparc/
F: target/sparc/
F: hw/sparc/
F: hw/sparc64/
F: disas/sparc.c
......@@ -226,7 +226,7 @@ F: disas/sparc.c
UniCore32
M: Guan Xuetao <gxt@mprc.pku.edu.cn>
S: Maintained
F: target-unicore32/
F: target/unicore32/
F: hw/unicore32/
F: include/hw/unicore32/
......@@ -235,7 +235,7 @@ M: Paolo Bonzini <pbonzini@redhat.com>
M: Richard Henderson <rth@twiddle.net>
M: Eduardo Habkost <ehabkost@redhat.com>
S: Maintained
F: target-i386/
F: target/i386/
F: hw/i386/
F: disas/i386.c
......@@ -243,14 +243,14 @@ Xtensa
M: Max Filippov <jcmvbkbc@gmail.com>
W: http://wiki.osll.spb.ru/doku.php?id=etc:users:jcmvbkbc:qemu-target-xtensa
S: Maintained
F: target-xtensa/
F: target/xtensa/
F: hw/xtensa/
F: tests/tcg/xtensa/
TriCore
M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
S: Maintained
F: target-tricore/
F: target/tricore/
F: hw/tricore/
F: include/hw/tricore/
......@@ -269,26 +269,26 @@ ARM
M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
S: Maintained
F: target-arm/kvm.c
F: target/arm/kvm.c
MIPS
M: James Hogan <james.hogan@imgtec.com>
S: Maintained
F: target-mips/kvm.c
F: target/mips/kvm.c
PPC
M: Alexander Graf <agraf@suse.de>
S: Maintained
F: target-ppc/kvm.c
F: target/ppc/kvm.c
S390
M: Christian Borntraeger <borntraeger@de.ibm.com>
M: Cornelia Huck <cornelia.huck@de.ibm.com>
M: Alexander Graf <agraf@suse.de>
S: Maintained
F: target-s390x/kvm.c
F: target-s390x/ioinst.[ch]
F: target-s390x/machine.c
F: target/s390x/kvm.c
F: target/s390x/ioinst.[ch]
F: target/s390x/machine.c
F: hw/intc/s390_flic.c
F: hw/intc/s390_flic_kvm.c
F: include/hw/s390x/s390_flic.h
......@@ -301,7 +301,7 @@ M: Paolo Bonzini <pbonzini@redhat.com>
M: Marcelo Tosatti <mtosatti@redhat.com>
L: kvm@vger.kernel.org
S: Supported
F: target-i386/kvm.c
F: target/i386/kvm.c
Guest CPU Cores (Xen):
----------------------
......
......@@ -155,11 +155,11 @@ trace-events-y += hw/alpha/trace-events
trace-events-y += ui/trace-events
trace-events-y += audio/trace-events
trace-events-y += net/trace-events
trace-events-y += target-arm/trace-events
trace-events-y += target-i386/trace-events
trace-events-y += target-sparc/trace-events
trace-events-y += target-s390x/trace-events
trace-events-y += target-ppc/trace-events
trace-events-y += target/arm/trace-events
trace-events-y += target/i386/trace-events
trace-events-y += target/sparc/trace-events
trace-events-y += target/s390x/trace-events
trace-events-y += target/ppc/trace-events
trace-events-y += qom/trace-events
trace-events-y += linux-user/trace-events
trace-events-y += qapi/trace-events
......@@ -11,7 +11,7 @@ $(call set-vpath, $(SRC_PATH):$(BUILD_DIR))
ifdef CONFIG_LINUX
QEMU_CFLAGS += -I../linux-headers
endif
QEMU_CFLAGS += -I.. -I$(SRC_PATH)/target-$(TARGET_BASE_ARCH) -DNEED_CPU_H
QEMU_CFLAGS += -I.. -I$(SRC_PATH)/target/$(TARGET_BASE_ARCH) -DNEED_CPU_H
QEMU_CFLAGS+=-I$(SRC_PATH)/include
......@@ -92,7 +92,7 @@ obj-$(CONFIG_TCG_INTERPRETER) += tci.o
obj-y += tcg/tcg-common.o
obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o
obj-y += fpu/softfloat.o
obj-y += target-$(TARGET_BASE_ARCH)/
obj-y += target/$(TARGET_BASE_ARCH)/
obj-y += disas.o
obj-y += tcg-runtime.o
obj-$(call notempty,$(TARGET_XML_FILES)) += gdbstub-xml.o
......
......@@ -21,9 +21,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "disas/bfd.h"
//#include "sysdep.h"
#include "target-cris/opcode-cris.h"
//#include "libiberty.h"
#include "target/cris/opcode-cris.h"
#define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
......
......@@ -3,7 +3,7 @@
#ifndef HW_ALPHA_SYS_H
#define HW_ALPHA_SYS_H
#include "target-alpha/cpu-qom.h"
#include "target/alpha/cpu-qom.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/ide.h"
......
......@@ -2,7 +2,7 @@
#define STRONGARM_H
#include "exec/memory.h"
#include "target-arm/cpu-qom.h"
#include "target/arm/cpu-qom.h"
#define SA_CS0 0x00000000
#define SA_CS1 0x08000000
......
......@@ -33,7 +33,7 @@
#include "qemu/bitmap.h"
#include "trace.h"
#include "qom/cpu.h"
#include "target-arm/cpu.h"
#include "target/arm/cpu.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/nvram/fw_cfg.h"
......
......@@ -29,7 +29,7 @@
#include "hw/pci/pci.h"
#include "qom/cpu.h"
#include "hw/i386/pc.h"
#include "target-i386/cpu.h"
#include "target/i386/cpu.h"
#include "hw/timer/hpet.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
......
......@@ -15,7 +15,7 @@
#include "hw/i386/apic_internal.h"
#include "hw/pci/msi.h"
#include "sysemu/kvm.h"
#include "target-i386/kvm_i386.h"
#include "target/i386/kvm_i386.h"
static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
int reg_id, uint32_t val)
......
......@@ -30,7 +30,7 @@
#include "hw/i386/ioapic_internal.h"
#include "include/hw/pci/msi.h"
#include "sysemu/kvm.h"
#include "target-i386/cpu.h"
#include "target/i386/cpu.h"
#include "hw/i386/apic-msidef.h"
#include "hw/i386/x86-iommu.h"
......
......@@ -17,7 +17,7 @@
#include "hw/qdev.h"
#include "hw/isa/isa.h"
#include "sysemu/kvm.h"
#include "target-i386/hyperv.h"
#include "target/i386/hyperv.h"
#include "kvm_i386.h"
#define HV_TEST_DEV_MAX_SINT_ROUTES 64
......
......@@ -9,7 +9,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "target-ppc/cpu.h"
#include "target/ppc/cpu.h"
#include "hw/ppc/fdt.h"
......
......@@ -22,7 +22,7 @@
#include "sysemu/sysemu.h"
#include "sysemu/numa.h"
#include "hw/hw.h"
#include "target-ppc/cpu.h"
#include "target/ppc/cpu.h"
#include "qemu/log.h"
#include "hw/ppc/fdt.h"
#include "hw/ppc/ppc.h"
......
......@@ -20,7 +20,7 @@
#include "sysemu/sysemu.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "target-ppc/cpu.h"
#include "target/ppc/cpu.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_core.h"
......
......@@ -19,7 +19,7 @@
#include "qemu/osdep.h"
#include "sysemu/sysemu.h"
#include "target-ppc/cpu.h"
#include "target/ppc/cpu.h"
#include "qapi/error.h"
#include "qemu/log.h"
......
......@@ -21,7 +21,7 @@
#include "hw/hw.h"
#include "qemu/log.h"
#include "sysemu/kvm.h"
#include "target-ppc/cpu.h"
#include "target/ppc/cpu.h"
#include "hw/sysbus.h"
#include "hw/ppc/fdt.h"
......
......@@ -8,14 +8,14 @@
*/
#include "hw/cpu/core.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "target-ppc/cpu.h"
#include "target/ppc/cpu.h"
#include "hw/ppc/spapr.h"
#include "hw/boards.h"
#include "qapi/error.h"
#include "sysemu/cpus.h"
#include "target-ppc/kvm_ppc.h"
#include "target/ppc/kvm_ppc.h"
#include "hw/ppc/ppc.h"
#include "target-ppc/mmu-hash64.h"
#include "target/ppc/mmu-hash64.h"
#include "sysemu/numa.h"
static void spapr_cpu_reset(void *opaque)
......
......@@ -25,7 +25,7 @@
Shix 2.0 board by Alexis Polti, described at
https://web.archive.org/web/20070917001736/perso.enst.fr/~polti/realisations/shix20
More information in target-sh4/README.sh4
More information in target/sh4/README.sh4
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
......
......@@ -12,7 +12,7 @@
#define HW_ARM_H
#include "exec/memory.h"
#include "target-arm/cpu-qom.h"
#include "target/arm/cpu-qom.h"
#include "hw/irq.h"
#include "qemu/notify.h"
......
......@@ -27,7 +27,7 @@
#include "qemu-common.h"
#include "exec/memory.h"
#include "target-arm/cpu-qom.h"
#include "target/arm/cpu-qom.h"
#define EXYNOS4210_NCPUS 2
......
......@@ -20,7 +20,7 @@
#include "exec/memory.h"
# define hw_omap_h "omap.h"
#include "hw/irq.h"
#include "target-arm/cpu-qom.h"
#include "target/arm/cpu-qom.h"
# define OMAP_EMIFS_BASE 0x00000000
# define OMAP2_Q0_BASE 0x00000000
......
......@@ -11,7 +11,7 @@
#define PXA_H
#include "exec/memory.h"
#include "target-arm/cpu-qom.h"
#include "target/arm/cpu-qom.h"
/* Interrupt numbers */
# define PXA2XX_PIC_SSP3 0
......
......@@ -2,7 +2,7 @@
#define HW_MCF_H
/* Motorola ColdFire device prototypes. */
#include "target-m68k/cpu-qom.h"
#include "target/m68k/cpu-qom.h"
struct MemoryRegion;
......
#ifndef HW_MIPS_CPUDEVS_H
#define HW_MIPS_CPUDEVS_H
#include "target-mips/cpu-qom.h"
#include "target/mips/cpu-qom.h"
/* Definitions for MIPS CPU internal devices. */
......
......@@ -11,7 +11,7 @@
#define PPC_FDT_H
#include "qemu/error-report.h"
#include "target-ppc/cpu-qom.h"
#include "target/ppc/cpu-qom.h"
#define _FDT(exp) \
do { \
......
#ifndef HW_PPC_H
#define HW_PPC_H
#include "target-ppc/cpu-qom.h"
#include "target/ppc/cpu-qom.h"
void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
......
......@@ -11,7 +11,7 @@
#include "hw/qdev.h"
#include "hw/cpu/core.h"
#include "target-ppc/cpu-qom.h"
#include "target/ppc/cpu-qom.h"
#define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
#define SPAPR_CPU_CORE(obj) \
......
......@@ -3,7 +3,7 @@
/* Definitions for SH board emulation. */
#include "hw/sh4/sh_intc.h"
#include "target-sh4/cpu-qom.h"
#include "target/sh4/cpu-qom.h"
#define A7ADDR(x) ((x) & 0x1fffffff)
#define P4ADDR(x) ((x) | 0xe0000000)
......
......@@ -48,7 +48,7 @@ grep_include() {
echo Found $(find . -name "*.d" | wc -l) object files
echo $(grep_include -F 'include/qemu-common.h') files include qemu-common.h
echo $(grep_include -F 'hw/hw.h') files include hw/hw.h
echo $(grep_include 'target-[a-z0-9]*/cpu\.h') files include cpu.h
echo $(grep_include 'target/[a-z0-9]*/cpu\.h') files include cpu.h
echo $(grep_include -F 'qapi-types.h') files include qapi-types.h
echo $(grep_include -F 'trace/generated-tracers.h') files include generated-tracers.h
echo $(grep_include -F 'qapi/error.h') files include qapi/error.h
......@@ -95,8 +95,8 @@ analyze -include ../include/qemu/osdep.h ../include/hw/hw.h
echo trace/generated-tracers.h:
analyze -include ../include/qemu/osdep.h trace/generated-tracers.h
echo target-i386/cpu.h:
analyze -DNEED_CPU_H -I../target-i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../target-i386/cpu.h
echo target/i386/cpu.h:
analyze -DNEED_CPU_H -I../target/i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../target/i386/cpu.h
echo hw/hw.h + NEED_CPU_H:
analyze -DNEED_CPU_H -I../target-i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../include/hw/hw.h
analyze -DNEED_CPU_H -I../target/i386 -Ii386-softmmu -include ../include/qemu/osdep.h ../include/hw/hw.h
......@@ -18,7 +18,7 @@
* <http://www.gnu.org/licenses/gpl-2.0.html>
*
* This header defines functions, types, etc which need to be shared
* between different source files within target-arm/ but which are
* between different source files within target/arm/ but which are
* private to it and not required by the rest of QEMU.
*/
......
# See docs/tracing.txt for syntax documentation.
# target-arm/helper.c
# target/arm/helper.c
arm_gt_recalc(int timer, int irqstate, uint64_t nexttick) "gt recalc: timer %d irqstate %d next tick %" PRIx64
arm_gt_recalc_disabled(int timer) "gt recalc: timer %d irqstate 0 timer disabled"
arm_gt_cval_write(int timer, uint64_t value) "gt_cval_write: timer %d value %" PRIx64
......