Commit a54238ad authored by Jose Ricardo Ziviani's avatar Jose Ricardo Ziviani Committed by David Gibson

ppc: Implement bcdsr. instruction

bcdsr.: Decimal shift and round. This instruction works like bcds.
however, when performing right shift, 1 will be added to the
result if the last digit was >= 5.
Signed-off-by: 's avatarJose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Signed-off-by: 's avatarDavid Gibson <david@gibson.dropbear.id.au>
parent a49a95e9
......@@ -395,6 +395,7 @@ DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xsaddqp, void, env, i32)
......
......@@ -3143,6 +3143,54 @@ uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
return cr;
}
uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
{
int cr;
int unused = 0;
int invalid = 0;
bool ox_flag = false;
int sgnb = bcd_get_sgn(b);
ppc_avr_t ret = *b;
ret.u64[LO_IDX] &= ~0xf;
#if defined(HOST_WORDS_BIGENDIAN)
int i = a->s8[7];
ppc_avr_t bcd_one = { .u64 = { 0, 0x10 } };
#else
int i = a->s8[8];
ppc_avr_t bcd_one = { .u64 = { 0x10, 0 } };
#endif
if (bcd_is_valid(b) == false) {
return CRF_SO;
}
if (unlikely(i > 31)) {
i = 31;
} else if (unlikely(i < -31)) {
i = -31;
}
if (i > 0) {
ulshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], i * 4, &ox_flag);
} else {
urshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], -i * 4);
if (bcd_get_digit(&ret, 0, &invalid) >= 5) {
bcd_add_mag(&ret, &ret, &bcd_one, &invalid, &unused);
}
}
bcd_put_digit(&ret, bcd_preferred_sgn(sgnb, ps), 0);
cr = bcd_cmp_zero(&ret);
if (ox_flag) {
cr |= CRF_SO;
}
*r = ret;
return cr;
}
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
......
......@@ -1018,6 +1018,7 @@ GEN_BCD2(bcdsetsgn)
GEN_BCD(bcdcpsgn);
GEN_BCD(bcds);
GEN_BCD(bcdus);
GEN_BCD(bcdsr);
static void gen_xpnd04_1(DisasContext *ctx)
{
......
......@@ -132,6 +132,8 @@ GEN_HANDLER_E_2(vprtybd, 0x4, 0x1, 0x18, 9, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E_2(vprtybq, 0x4, 0x1, 0x18, 10, 0, PPC_NONE, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_300(bcdsr, 0, 23),
GEN_VXFORM_300(bcdsr, 0, 31),
GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vadduws, 0, 10),
......
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