Commit 25156d10 authored by Michael Walle's avatar Michael Walle

lm32: remove lm32_sys

Since we have now semihosting on the lm32 target, this device is no longer
needed. Remove it.
Signed-off-by: 's avatarMichael Walle <michael@walle.cc>
parent 4e7d30a2
......@@ -29,7 +29,6 @@ obj-$(CONFIG_NSERIES) += cbus.o
obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o
obj-$(CONFIG_IMX) += imx_ccm.o
obj-$(CONFIG_LM32) += lm32_sys.o
obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
obj-$(CONFIG_MAINSTONE) += mst_fpga.o
......
/*
* QEMU model of the LatticeMico32 system control block.
*
* Copyright (c) 2010 Michael Walle <michael@walle.cc>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
/*
* This model is mainly intended for testing purposes and doesn't fit to any
* real hardware. On the one hand it provides a control register (R_CTRL) on
* the other hand it supports the lm32 tests.
*
* A write to the control register causes a system shutdown.
* Tests first write the pointer to a test name to the test name register
* (R_TESTNAME) and then write a zero to the pass/fail register (R_PASSFAIL) if
* the test is passed or any non-zero value to it if the test is failed.
*/
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "trace.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "sysemu/sysemu.h"
enum {
R_CTRL = 0,
R_PASSFAIL,
R_TESTNAME,
R_MAX
};
#define MAX_TESTNAME_LEN 32
#define TYPE_LM32_SYS "lm32-sys"
#define LM32_SYS(obj) OBJECT_CHECK(LM32SysState, (obj), TYPE_LM32_SYS)
struct LM32SysState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t base;
uint32_t regs[R_MAX];
uint8_t testname[MAX_TESTNAME_LEN];
};
typedef struct LM32SysState LM32SysState;
static void copy_testname(LM32SysState *s)
{
cpu_physical_memory_read(s->regs[R_TESTNAME], s->testname,
MAX_TESTNAME_LEN);
s->testname[MAX_TESTNAME_LEN - 1] = '\0';
}
static void sys_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
LM32SysState *s = opaque;
char *testname;
trace_lm32_sys_memory_write(addr, value);
addr >>= 2;
switch (addr) {
case R_CTRL:
qemu_system_shutdown_request();
break;
case R_PASSFAIL:
s->regs[addr] = value;
testname = (char *)s->testname;
fprintf(stderr, "TC %-*s %s\n", MAX_TESTNAME_LEN,
testname, (value) ? "FAILED" : "OK");
if (value) {
cpu_dump_state(qemu_get_cpu(0), stderr, fprintf, 0);
}
break;
case R_TESTNAME:
s->regs[addr] = value;
copy_testname(s);
break;
default:
error_report("lm32_sys: write access to unknown register 0x"
TARGET_FMT_plx, addr << 2);
break;
}
}
static bool sys_ops_accepts(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return is_write && size == 4;
}
static const MemoryRegionOps sys_ops = {
.write = sys_write,
.valid.accepts = sys_ops_accepts,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void sys_reset(DeviceState *d)
{
LM32SysState *s = LM32_SYS(d);
int i;
for (i = 0; i < R_MAX; i++) {
s->regs[i] = 0;
}
memset(s->testname, 0, MAX_TESTNAME_LEN);
}
static int lm32_sys_init(SysBusDevice *dev)
{
LM32SysState *s = LM32_SYS(dev);
memory_region_init_io(&s->iomem, OBJECT(dev), &sys_ops , s,
"sys", R_MAX * 4);
sysbus_init_mmio(dev, &s->iomem);
/* Note: This device is not created in the board initialization,
* instead it has to be added with the -device parameter. Therefore,
* the device maps itself. */
sysbus_mmio_map(dev, 0, s->base);
return 0;
}
static const VMStateDescription vmstate_lm32_sys = {
.name = "lm32-sys",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, LM32SysState, R_MAX),
VMSTATE_BUFFER(testname, LM32SysState),
VMSTATE_END_OF_LIST()
}
};
static Property lm32_sys_properties[] = {
DEFINE_PROP_UINT32("base", LM32SysState, base, 0xffff0000),
DEFINE_PROP_END_OF_LIST(),
};
static void lm32_sys_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = lm32_sys_init;
dc->reset = sys_reset;
dc->vmsd = &vmstate_lm32_sys;
dc->props = lm32_sys_properties;
}
static const TypeInfo lm32_sys_info = {
.name = TYPE_LM32_SYS,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LM32SysState),
.class_init = lm32_sys_class_init,
};
static void lm32_sys_register_types(void)
{
type_register_static(&lm32_sys_info);
}
type_init(lm32_sys_register_types)
......@@ -16,16 +16,6 @@ This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.
Programmatically terminate the emulator
----------------------------------------
Originally neither the LatticeMico32 nor its peripherals support a
mechanism to shut down the machine. Emulation aware programs can write to a
to a special register within the system control block to shut down the
virtual machine. For more details see hw/lm32_sys.c. The lm32-evr is the
first BSP which instantiate this model. A (32 bit) write to 0xfff0000
causes a vm shutdown.
Semihosting
-----------
Semihosting on this target is supported. Some system calls like read, write
......
......@@ -627,9 +627,6 @@ lm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
lm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
lm32_uart_irq_state(int level) "irq state %d"
# hw/misc/lm32_sys.c
lm32_sys_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
# hw/scsi/megasas.c
megasas_init_firmware(uint64_t pa) "pa %" PRIx64 " "
megasas_init_queue(uint64_t queue_pa, int queue_len, uint64_t head, uint64_t tail, uint32_t flags) "queue at %" PRIx64 " len %d head %" PRIx64 " tail %" PRIx64 " flags %x"
......
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