• Suraj Jitindar Singh's avatar
    target/ppc: Implement ISA V3.00 radix page fault handler · d5fee0bb
    Suraj Jitindar Singh authored
    ISA V3.00 introduced a new radix mmu model. Implement the page fault
    handler for this so we can run a tcg guest in radix mode and perform
    address translation correctly.
    
    In real mode (mmu turned off) addresses are masked to remove the top
    4 bits and then are subject to partition scoped translation, since we only
    support pseries at this stage it is only necessary to perform the masking
    and then we're done.
    
    In virtual mode (mmu turned on) address translation if performed as
    follows:
    
    1. Use the quadrant to determine the fully qualified address.
    
    The fully qualified address is defined as the combination of the effective
    address, the effective logical partition id (LPID) and the effective
    process id (PID). Based on the quadrant (EA63:62) we set the pid and lpid
    like so:
    
    quadrant 0: lpid = LPIDR, pid = PIDR
    quadrant 1: HV only (not allowed in pseries)
    quadrant 2: HV only (not allowed in pseries)
    quadrant 3: lpid = LPIDR, pid = 0
    
    If we can't get the fully qualified address we raise a segment interrupt.
    
    2. Find the guest radix tree
    
    We ask the virtual hypervisor for the partition table which was registered
    with H_REGISTER_PROC_TBL which points us to the process table in guest
    memory. We then index this table by pid to get the process table entry
    which points us to the appropriate radix tree to translate the address.
    
    If the process table isn't big enough to contain an entry for the current
    pid then we raise a storage interrupt.
    
    3. Walk the radix tree
    
    Next we walk the radix tree where each level is a table of page directory
    entries indexed by some number of bits from the effective address, where
    the number of bits is determined by the table size. We continue to walk
    the tree (while entries are valid and the table is of minimum size) until
    we reach a table of page table entries, indicated by having the leaf bit
    set. The appropriate pte is then checked for sufficient access permissions,
    the reference and change bits are updated and the real address is
    calculated from the real page number bits of the pte and the low bits of
    the effective address.
    
    If we can't find an entry or can't access the entry bacause of permissions
    then we raise a storage interrupt.
    Signed-off-by: 's avatarSuraj Jitindar Singh <sjitindarsingh@gmail.com>
    [dwg: Add missing parentheses to macro]
    Signed-off-by: 's avatarDavid Gibson <david@gibson.dropbear.id.au>
    d5fee0bb
mmu-book3s-v3.c 1.27 KB