• Stafford Horne's avatar
    target/openrisc: implement shadow registers · d89e71e8
    Stafford Horne authored
    Shadow registers are part of the openrisc spec along with sr[cid], as
    part of the fast context switching feature.  When exceptions occur,
    instead of having to save registers to the stack if enabled the CID will
    increment and a new set of registers will be available.
    
    This patch only implements shadow registers which can be used as extra
    scratch registers via the mfspr and mtspr if required.  This is
    implemented in a way where it would be easy to add on the fast context
    switching, currently cid is hardcoded to 0.
    
    This is need for openrisc linux smp kernels to boot correctly.
    Signed-off-by: 's avatarStafford Horne <shorne@gmail.com>
    d89e71e8
translate.c 46.3 KB